1. Field of the Invention
The present invention relates to a delay circuit, and in particular to an improved delay circuit which is capable of having a constant time with respect to an externally applied voltage.
2. Description of the Conventional Art
As shown in FIG. 1, the conventional delay circuit includes a plurality of series inverters IN1 through INn, and a plurality of NMOS transistors NM1' through NMn-1' the drains and sources of which are commonly connected with a ground voltage VSS, respectively.
Each of the inverters IN1 through INn includes a corresponding one of PMOS transistors PM1 through PMn and a corresponding one of NMOS transistors NM1 through NMn the gates of which are commonly connected in series between an externally applied voltage VCC and a ground voltage VSS, thus forming an input terminal, and the drains of which are commonly connected, thus forming an output terminal.
The operation of the conventional delay circuit will now be explained with reference to FIGS. 1 and 2.
First, when an input signal VI is transited from a low level to a high level, the NMOS transistor NM1 of the first inverter IN1 is turned on.
At this time, the transition time of the output signal from the inverter IN1 is determined based on a value which is obtained through a multiplication between an Effective On Resistance of the NMOS transistor NM1 and an Effective Capacitance of the output terminal, so that it is possible to output an output voltage VO delayed more than the input voltage VI using the above-described transition time.
Here, the effective capacitance of the output terminal of the inverter is a sum between the signal value from the MOS transistor of the first inverter IN1 and a gate capacitance from an inverter IN2 of the next circuit.
As shown in FIG. 2, in the conventional delay circuit, as the externally applied voltage VCC is decreased, the effective capacitance value maintains a predetermined level. In addition, since the Effective On Resistance is increased, the delay time is determined by the time constant RC, so that the delay time is increased because the Effective On Resistance is reverse-proportional to the difference between the electric potential difference Vgs between the gate and the source and a threshold voltage Vth. Therefore, as the externally applied voltage VCC is increased, the electric potential of the gate is increased, and the Effective On Resistance is decreased, so that the delay time is decreased.
This is, as the externally applied voltage VCC is increased, the delay time is decreased.